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Senior Verification Engineer - UVM / SystemVerilog

European Tech Recruit · EMEA

  • Hybrid
  • Contract
  • $120,000 / year
  • EMEA

Job highlights

  • Design complex microprocessor architectures verification.
  • Develop UVM/SystemVerilog testbenches.
  • Collaborate with cross-functional teams.
  • Flexible remote or onsite work.
  • Career growth and development opportunities.

About the role

Senior Verification Engineer - UVM / SystemVerilog

We are working with an innovative semiconductor company at the forefront of high-performance processor design, currently looking to hire multiple Senior Verification Engineers to support the development of complex microprocessor architectures. This is an opportunity to join a highly technical environment where verification plays a critical role in delivering cutting-edge silicon solutions. The role can either be undertaken on a fully remote basis, working as a contractor or 100% onsite in Barcelona, on a preferment employment basis.

The Role

As part of the Verification team, you will be responsible for ensuring the correctness and functionality of advanced digital designs at RTL level. You will work closely with design and architecture teams, applying modern verification methodologies to validate complex processor-based systems.

Key Responsibilities

  • Develop and execute verification plans for complex ASIC / SoC designs
  • Build and maintain SystemVerilog UVM-based testbenches
  • Perform block, subsystem, and full-chip level verification
  • Run simulations, debug failures, and analyse coverage
  • Contribute to both dynamic and formal verification strategies
  • Collaborate with cross-functional engineering teams

Requirements

  • Master’s or PhD in Electronics, Computer Engineering, or similar
  • 5+ years of experience in hardware / ASIC verification
  • Strong expertise in SystemVerilog and UVM
  • Solid experience with RTL verification methodologies
  • Familiarity with scripting languages such as Python, Perl, Bash, or TCL
  • Experience with simulation tools and regression environments
  • Understanding of version control tools such as Git or SVN
  • Exposure to formal verification techniques
  • Strong problem-solving and debugging skills
  • Fluent English (C1 level or above)

What’s on Offer

  • Flexible working arrangements (remote or onsite in Barcelona)
  • Visa sponsorship available (for onsite work only) - you must have the Right to work for the country in which you reside
  • Highly collaborative and technical environment
  • Strong learning and career development opportunities

Key skills/competency

  • Verification Engineering
  • UVM
  • SystemVerilog
  • ASIC Verification
  • RTL Verification
  • SoC Design
  • Formal Verification
  • Python
  • Debugging
  • Hardware Verification

Skills & topics

  • Senior Verification Engineer
  • UVM
  • SystemVerilog
  • ASIC Verification
  • RTL Verification
  • SoC Design
  • Hardware Verification
  • FPGA
  • Digital Design
  • Semiconductor

How to get hired

  • Tailor your resume: Highlight your 5+ years of ASIC verification experience, SystemVerilog, and UVM expertise. Quantify achievements where possible.
  • Showcase technical skills: Emphasize your proficiency in RTL verification methodologies, scripting languages (Python, Perl), and simulation tools.
  • Address the role requirements: Clearly state your Master's/PhD and fluency in English (C1+). Mention any experience with formal verification.
  • Express interest in location: Specify if you are seeking a remote contractor role or an onsite employment role in Barcelona.
  • Apply promptly: Click the link to apply or email your CV directly to smouland@eu-recruit.com to expedite your application.

Technical preparation

Master UVM testbench development.,Practice SystemVerilog for verification.,Scripting: Python, Perl, Bash, TCL.,Familiarize with Git/SVN and simulators.

Behavioral questions

Describe a complex verification challenge.,How do you debug complex failures?,How do you collaborate with design teams?,Discuss your experience with formal verification.

Frequently asked questions

What is the work arrangement for the Senior Verification Engineer role at European Tech Recruit?
The Senior Verification Engineer role offers flexible working arrangements. You can choose to work remotely as a contractor or 100% onsite in Barcelona as a preferred employee. Visa sponsorship is available for onsite work.
What are the primary responsibilities of a Senior Verification Engineer with UVM/SystemVerilog?
As a Senior Verification Engineer, you will develop and execute verification plans for complex ASIC/SoC designs, build SystemVerilog UVM testbenches, perform block, subsystem, and full-chip level verification, run simulations, debug failures, analyze coverage, and contribute to dynamic and formal verification strategies.
What are the minimum educational and experience requirements for this role?
Candidates must possess a Master’s or PhD in Electronics, Computer Engineering, or a similar field, with at least 5 years of experience in hardware/ASIC verification. Strong expertise in SystemVerilog and UVM is essential.
Does European Tech Recruit offer visa sponsorship for the Senior Verification Engineer position?
Yes, visa sponsorship is available for candidates applying for the onsite role in Barcelona. This sponsorship is specifically for the onsite employment basis.
What technical skills are most important for the Senior Verification Engineer role?
The most critical technical skills include strong expertise in SystemVerilog and UVM, solid experience with RTL verification methodologies, familiarity with scripting languages like Python or Perl, and experience with simulation tools and regression environments.
How can I apply for the Senior Verification Engineer job at European Tech Recruit?
You can apply for the Senior Verification Engineer position by clicking the provided link or by emailing your CV directly to smouland@eu-recruit.com.
What level of English proficiency is required for this role?
A fluent English level, specifically C1 or above, is required for the Senior Verification Engineer position.
What are the benefits of working as a Senior Verification Engineer at this company?
The role offers flexible working, a highly collaborative and technical environment, strong learning and career development opportunities, and visa sponsorship for onsite work in Barcelona.