23 days ago

Senior Verification Engineer

European Tech Recruit

Hybrid
Contractor
$120,000
Hybrid

Job Overview

Job TitleSenior Verification Engineer
Job TypeContractor
Offered Salary$120,000
LocationHybrid
Map of Hybrid

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Job Description

Senior Verification Engineer - UVM / SystemVerilog

We are working with an innovative semiconductor company at the forefront of high-performance processor design, currently looking to hire multiple Senior Verification Engineers to support the development of complex microprocessor architectures. This is an opportunity to join a highly technical environment where verification plays a critical role in delivering cutting-edge silicon solutions. The role can either be undertaken on a fully remote basis, working as a contractor or 100% onsite in Barcelona, on a preferment employment basis.

The Role

As part of the Verification team, you will be responsible for ensuring the correctness and functionality of advanced digital designs at RTL level. You will work closely with design and architecture teams, applying modern verification methodologies to validate complex processor-based systems.

Key Responsibilities

  • Develop and execute verification plans for complex ASIC / SoC designs
  • Build and maintain SystemVerilog UVM-based testbenches
  • Perform block, subsystem, and full-chip level verification
  • Run simulations, debug failures, and analyse coverage
  • Contribute to both dynamic and formal verification strategies
  • Collaborate with cross-functional engineering teams

Requirements

  • Master’s or PhD in Electronics, Computer Engineering, or similar
  • 5+ years of experience in hardware / ASIC verification
  • Strong expertise in SystemVerilog and UVM
  • Solid experience with RTL verification methodologies
  • Familiarity with scripting languages such as Python, Perl, Bash, or TCL
  • Experience with simulation tools and regression environments
  • Understanding of version control tools such as Git or SVN
  • Exposure to formal verification techniques
  • Strong problem-solving and debugging skills
  • Fluent English (C1 level or above)

What’s on Offer

  • Flexible working arrangements (remote or onsite in Barcelona)
  • Visa sponsorship available (for onsite work only) - you must have the Right to work for the country in which you reside
  • Highly collaborative and technical environment
  • Strong learning and career development opportunities

Key skills/competency

  • Verification Engineering
  • UVM
  • SystemVerilog
  • ASIC Verification
  • RTL Verification
  • SoC Design
  • Formal Verification
  • Python
  • Debugging
  • Hardware Verification

Tags:

Senior Verification Engineer
UVM
SystemVerilog
ASIC Verification
RTL Verification
SoC Design
Hardware Verification
FPGA
Digital Design
Semiconductor

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How to Get Hired at European Tech Recruit

  • Tailor your resume: Highlight your 5+ years of ASIC verification experience, SystemVerilog, and UVM expertise. Quantify achievements where possible.
  • Showcase technical skills: Emphasize your proficiency in RTL verification methodologies, scripting languages (Python, Perl), and simulation tools.
  • Address the role requirements: Clearly state your Master's/PhD and fluency in English (C1+). Mention any experience with formal verification.
  • Express interest in location: Specify if you are seeking a remote contractor role or an onsite employment role in Barcelona.
  • Apply promptly: Click the link to apply or email your CV directly to smouland@eu-recruit.com to expedite your application.

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