Senior UVM Digital Verification Engineer
@ Draper

Cambridge, MA
$205,750
On Site
Full Time
Posted 1 day ago

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Job Details

Overview

Draper is an independent nonprofit research and development company headquartered in Cambridge, MA. With 2,000+ employees, Draper tackles important national challenges across military defense, space exploration, biomedical engineering and more. Visit draper.com for more information.

Job Description Summary

The Senior UVM Digital Verification Engineer will develop verification strategies for FPGAs and ASICs. This role involves working on complex digital and mixed-signal designs in embedded security, cryptography, signal and image processing, navigation, and communications.

Duties and Responsibilities

  • Perform analysis and execute assignments independently.
  • Lead small teams and align them with program goals.
  • Drive solutions and propose design modifications.
  • Identify and mitigate program/system-level technical risks.
  • Mentor junior engineers and collaborate with multidisciplinary teams.
  • Translate requirements into technical decisions.

Key Skills/Competency

  • UVM
  • System Verilog
  • Verification
  • FPGA
  • ASIC
  • Simulation
  • MATLAB
  • Linux
  • Python
  • Team Leadership

Additional Information

The role also involves developing verification plans, working with formal analysis tools, and collaborating with RTL designers. Candidates should be adept with simulation tools like Questasim, Xcelium, or VCS and have experience with DDR3/DDR4, Amba AXI protocols, and scripting languages. A government security clearance is required or must be obtainable.

Draper promotes work-life balance with flexible work hours, various employee clubs, and social events.

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How to Get Hired at Draper

🎯 Tips for Getting Hired

  • Customize Your Resume: Tailor skills to Draper's job requirements.
  • Show Practical Experience: Emphasize UVM and System Verilog projects.
  • Prepare for Technical Interviews: Review FPGA and ASIC verification challenges.
  • Research Draper's Culture: Understand their R&D mission and multidisciplinary work.

📝 Interview Preparation Advice

Technical Preparation

Review UVM and System Verilog basics.
Practice FPGA/ASIC simulation scenarios.
Familiarize with DDR and AXI protocols.
Study formal verification and scripting tools.

Behavioral Questions

Describe a difficult team project.
Explain how you handle tight deadlines.
Share a time when you mentored others.
Discuss adapting to changing priorities.

Frequently Asked Questions