ASIC Design Engineering Technical Lead (Hybrid)
Cisco · San Jose, CA
- On site
- Full-time
- $263,600 / year
- San Jose, CA
Job highlights
- Lead ASIC subsystem design and end-to-end ownership.
- Develop high-performance RTL in Verilog/SystemVerilog.
- Collaborate with cross-functional engineering teams.
- Mentor engineers and drive technical execution.
- Tackle complex challenges in hyperscale silicon.
About the role
ASIC Design Engineering Technical Lead at Cisco
Cisco Silicon One is seeking a highly specialized ASIC team member to join their group. This team is responsible for developing programmable, scalable silicon architectures that power next-generation networking products. Join us to shape Cisco's ground-breaking solutions by designing, developing, and testing some of the most complex ASICs in the industry.
Your Impact
As an ASIC Design Engineering Technical Lead, you will have end-to-end ownership of ASIC subsystems. You will contribute to a multi-disciplinary engineering team to achieve power, performance, and area goals for products. You will also help define the processes, methods, and tools for complex development projects, tackling some of the most challenging problems in high-performance silicon for hyperscale infrastructure.
- Design and implement high-frequency, high-performance RTL in Verilog / System Verilog, meeting aggressive timing, power, and area targets.
- Lead design specifications and technical reviews, ensuring architectural clarity and high-quality implementation.
- Drive technical execution across architecture, design, verification, and physical implementation teams to deliver robust silicon.
- Collaborate closely with verification and physical design teams to close functional coverage, timing, and integration challenges.
- Mentor engineers and elevate engineering rigor, design quality, and technical execution across the team.
- Lead debug and root-cause analysis across simulation, system bring-up, and post-silicon validation.
- Create re-usable code that promotes efficiencies in new ways.
- Influence system architecture and key design decisions across complex ASIC subsystems.
Minimum Qualifications
- Bachelor's degree in Electrical Engineering with 8+ years of ASIC design experience, or Master's degree in Electrical Engineering with 6+ years of ASIC design experience, or PhD in Electrical Engineering and 3+ years of ASIC design experience.
- ASIC design experience, delivering silicon from microarchitecture, specification, and RTL coding through tape-out with multiple ASIC tape-outs at advanced technology nodes.
- Strong expertise in high-performance RTL design using Verilog/SystemVerilog.
- Deep understanding of timing closure, power optimization, and clock gating techniques.
- Experience with ASIC development flows including simulation, synthesis, and static timing analysis.
Preferred Qualifications
- 10+ years of ASIC design experience, delivering silicon from architecture and specification through tape-out.
- Strong documentation, problem-solving, debug and technical communication skills.
- Experience working cross-functionally and collaborating with various technical teams.
- Problem solver who loves to tackle new challenges and a self-starter who is highly motivated and thrives on innovative technology.
- Strong communicator in a team setting, enjoys working in a dynamic team environment, and is an out-of-the-box thinker.
Why Cisco?
At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you.
Key skills/competency
- ASIC Design
- Technical Lead
- RTL Design
- Verilog
- SystemVerilog
- Timing Closure
- Power Optimization
- ASIC Development Flows
- Electrical Engineering
- Silicon Architecture
Skills & topics
- ASIC Design
- Technical Lead
- RTL Design
- Verilog
- SystemVerilog
- Electrical Engineering
- Silicon One
- Networking ASICs
- Timing Closure
- Power Optimization
How to get hired
- Tailor your resume: Highlight your ASIC design experience, RTL coding skills (Verilog/SystemVerilog), and success in meeting timing, power, and area targets. Emphasize your leadership and mentorship experience.
- Showcase your expertise: Prepare to discuss your experience with the full ASIC development flow, from microarchitecture and specification to tape-out at advanced technology nodes.
- Demonstrate problem-solving skills: Be ready to share examples of how you've tackled complex silicon challenges, led debug efforts, and influenced architectural decisions.
- Highlight collaboration: Provide instances where you've successfully worked with verification and physical design teams to achieve project goals.
- Research Cisco's culture: Understand Cisco's commitment to innovation, collaboration, and revolutionizing data infrastructure to align your answers with their values.
Technical preparation
Behavioral questions
Frequently asked questions
- What is the application deadline for the ASIC Design Engineering Technical Lead role at Cisco?
- The application window for the ASIC Design Engineering Technical Lead position at Cisco is expected to close on May 29, 2026. However, please note that the posting may be removed earlier if the position is filled or if a sufficient number of applications are received.
- What are the remote work options for the ASIC Design Engineering Technical Lead position at Cisco?
- This ASIC Design Engineering Technical Lead position is a hybrid role. You are required to live within commuting distance of the San Jose, CA office and commute to the office 4-5 days per week.
- What is the required educational background for the ASIC Design Engineering Technical Lead at Cisco?
- The minimum educational requirement is a Bachelor's degree in Electrical Engineering with 8+ years of ASIC design experience. Alternatively, a Master's degree with 6+ years or a PhD with 3+ years of relevant experience is also acceptable.
- What programming languages are primarily used for RTL design in this role at Cisco?
- For this ASIC Design Engineering Technical Lead role at Cisco, strong expertise in high-performance RTL design using Verilog and SystemVerilog is required.
- What kind of networking products does Cisco Silicon One develop ASICs for?
- Cisco Silicon One develops ASICs for a wide range of Cisco platforms, driving the world's most complex networks. These silicon devices handle over 90% of IP traffic and are used from Top of Rack switches through web-scale data centers, spanning service provider, enterprise networks, and data centers with a unified routing and switching portfolio.
- What are the key responsibilities of an ASIC Design Engineering Technical Lead at Cisco?
- Key responsibilities include defining and designing ASIC subsystems, leading technical reviews, driving execution across design and verification teams, mentoring junior engineers, and leading debug and root-cause analysis.
- What are the salary expectations for the ASIC Design Engineering Technical Lead position in the US?
- The starting salary range for this position in U.S. locations is $183,800.00 to $263,600.00, not including potential incentive compensation, equity, or benefits. Specific compensation is determined by factors like hiring location, experience, and qualifications.
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