Digital Design Verification Engineer
@ Capgemini

Santa Clara, California, United States
On Site
Full-time
Posted 9 days ago

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Job Details

About the Job You’re Considering

We’re looking for a collaborative Digital Design Verification Engineer to help shape the future of SoC development. In this role, you’ll contribute to the validation of high-performance ARM-based systems, working across digital domains. You’ll join a supportive team that values diverse perspectives, continuous learning, and innovative problem-solving.

Your Role

  • Develop and implement verification environments using SystemVerilog and UVM for IPs and SoCs with embedded CPUs.
  • Create detailed test plans and coverage metrics from design specifications and execute both block- and chip-level tests.
  • Collaborate with design engineers to analyze and resolve RTL and gate-level simulation issues.
  • Partner with architects to simulate real-world use cases and ensure system-level functionality.

Your Skills and Experience

  • Bachelor’s degree or higher in Electrical or Computer Engineering, with 5+ years of experience.
  • Deep expertise in SystemVerilog, UVM, and SV Assertions, with a strong foundation in Verilog-HDL and scripting.
  • Strong analytical and communication skills, with a self-driven, collaborative approach to problem-solving and automation using Python and PERL.

Life at Capgemini

Capgemini supports all aspects of your well-being throughout the changing stages of your life and career. For eligible employees, we offer:

  • Flexible work
  • Healthcare including dental, vision, mental health, and well-being programs
  • Financial well-being programs such as 401(k) and Employee Share Ownership Plan
  • Paid time off and paid holidays
  • Paid parental leave
  • Family building benefits like adoption assistance, surrogacy, and cryopreservation
  • Social well-being benefits like subsidized back-up child/elder care and tutoring
  • Mentoring, coaching and learning programs
  • Employee Resource Groups
  • Disaster Relief

About Capgemini Engineering

World leader in engineering and R&D services, Capgemini Engineering combines its broad industry knowledge and cutting-edge technologies in digital and software to support the convergence of the physical and digital worlds. Coupled with the capabilities of the rest of the Group, it helps clients to accelerate their journey towards Intelligent Industry.

How to Get Hired at Capgemini

🎯 Tips for Getting Hired

  • Customize your resume: Tailor your resume to highlight relevant skills in SystemVerilog and UVM.
  • Network with Capgemini employees: Connect on LinkedIn for insights and referrals.
  • Prepare for technical interviews: Brush up on ARM architecture and verification methodologies.
  • Research Capgemini's projects: Familiarize yourself with their engineering services and recent innovations.

📝 Interview Preparation Advice

Technical Preparation

Master SystemVerilog and UVM concepts.
Practice creating test plans from specifications.
Learn to analyze RTL and gate-level simulations.
Familiarize with ARM architecture functionalities.

Behavioral Questions

Prepare to discuss team collaboration experiences.
Think of times you solved complex problems.
Reflect on your adaptability in new projects.
Practice discussing your communication style.

Frequently Asked Questions