Digital Design Verification Engineer @ Capgemini
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About the Digital Design Verification Engineer Position
Capgemini is looking for a collaborative Digital Design Verification Engineer to shape the future of SoC development. In this role, you will contribute to the validation of high-performance ARM-based systems across digital domains within a supportive team that values diverse perspectives and continuous learning.
Your Role
You will develop and implement verification environments using SystemVerilog and UVM for IPs and SoCs with embedded CPUs, create detailed test plans and coverage metrics from design specifications, and execute both block- and chip-level tests.
You will also collaborate with design engineers to analyze and resolve RTL and gate-level simulation issues and partner with architects to simulate real-world use cases ensuring system-level functionality.
Your Skills and Experience
- Bachelor’s degree or higher in Electrical or Computer Engineering
- 5+ years of experience in digital design verification
- Expertise in SystemVerilog, UVM, and SV Assertions
- Strong foundation in Verilog-HDL and scripting languages like Python and PERL
- Excellent analytical and communication skills with a self-driven, collaborative mindset
Life at Capgemini
Capgemini offers a range of employee benefits including flexible work arrangements, healthcare coverage, financial well-being programs, generous paid time off and holidays, and family building benefits. Additional perks include mentoring, coaching, employee resource groups, and disaster relief support.
About Capgemini Engineering
Capgemini Engineering is a global leader in engineering and R&D services with a rich heritage and a presence in over 30 countries. The organization combines its extensive industry knowledge with cutting-edge technologies to drive impactful solutions for clients across various sectors including aerospace, defense, automotive, and more.
Key Skills/Competency
- SystemVerilog
- UVM
- SoC
- Design Verification
- RTL
- Gate-level Simulation
- IP Validation
- Python
- PERL
- Test Plan Development
How to Get Hired at Capgemini
🎯 Tips for Getting Hired
- Customize resume: Tailor your skills to digital design verification.
- Highlight experience: Emphasize SystemVerilog and UVM expertise.
- Prepare portfolio: Showcase past SoC or IP projects.
- Practice interviews: Research Capgemini and review technical topics.