ASIC/FPGA Design and Verification Engineer

Introduction to Boeing Electronic Products

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Boeing Space, Intelligence & Weapons Systems has an exciting opportunity for multiple ASIC/FPGA Design and Verification Engineers to join our Boeing Electronic Products team in Mountain View, CA. Our group develops ASICs and FPGAs that are at the heart of Boeing’s products, from complex digitally beamformed phased arrays for constellation satellite programs to computing and networking equipment for commercial airplanes.

We leverage leading-edge technology and work with world-class partners to provide some of the most complex SoCs in the world. We develop robust, high-performance custom processors using the latest ARM IP to enable high-integrity, low SWAP-C flight computers. Our diverse development portfolio provides opportunities to learn with exposure to the breadth of the Boeing product line, approximately half our design work is within the Space & Launch business unit, and half is from other parts of Boeing (AvionX; Missiles & Weapons; Strike, Surveillance and Mobility; and Autonomous Systems).

As an ASIC/FPGA Design and Verification Engineer on the Boeing Electronic Products team, you will develop state-of-the-art digital ICs/SoCs to support the most critical programs across the enterprise. We are hiring design and verification engineers at every level as we are only limited by our bandwidth for new projects. We collaborate with other electronics groups across the company and around the world, supporting ASIC/FPGA design and verification for electronics built in El Segundo or units designed at other sites.

Position Responsibilities

• Collaborate with customers, system engineers, and hardware engineers to drive requirements capture and architect digital logic functions to meet mission/customer needs.
• Explore trade-space of potential ASIC/FPGA technologies and determine optimal parts, weighing Schedule, Cost, Risk, Area, Power (SCRAP) vs. performance.
• Implement FPGA/ASIC with latest design practices and tools from block-level micro-architecture, through HDL coding, and physical design realization (through gate-level netlists for ASIC designs).
• Integrate DSP IP from Boeing’s algorithm team and third-party IP as needed.
• Perform static timing analysis, LEC, CDC, linting, and other necessary checks to ensure the design is completed on schedule.
• Develop Functional Coverage Models and perform Code Coverage to verify designs in simulation.
• Create self-checking and reusable test benches from scratch, applying Object-Oriented Programming concepts such as Inheritance and Polymorphism, and leverage UVM to create drivers, monitors, predictors, and scoreboards.
• Drive FPGA-based prototyping and validation depending on program and system requirements and complexity.
• Validate design through hardware integration test with special test equipment, test-beds, and higher-level systems as needed.

Basic Qualifications (Required Skills/Experience)

• Bachelor of Science degree in Engineering (with a focus in Electrical, Mechanical or Aeronautical), Computer Science, Data Science, Mathematics, Physics, Chemistry or non-US equivalent qualifications directly related to the work statement.
• ASIC/FPGA design or verification knowledge.

Preferred Qualifications (Desired Skills/Experience)

• Associate, Level 2: 2+ years of related work experience.
• Experienced, Level 3: 5+ years of related work experience.
• Master's Degree in EE, Computer Engineering/Science, or related field, or equivalent experience.
• Experience with ASIC/FPGA architectural definition, and detailed design implementation and functional verification using SystemVerilog with delivery/release of production designs.
• Experience with hardware emulators, especially Palladium.
• Proficiency with hardware verification languages: SystemVerilog, SystemVerilog Assertions.
• Ability to executable test plans.
• Proficiency with Object-Oriented Programming Concepts: Inheritance, Polymorphism, etc.
• Ability to create self-checking and reusable testbenches from scratch.
• Experience developing Functional Coverage Models and Closing Code Coverage.
• Experience with high-speed Serdes interfaces (JESD204C, PCIe, Ethernet).
• Proficient in scripting languages: Make, Perl, Python, etc.
• Revision Control Systems: svn, cvs, git.
• Proficient in Linux Environments.
• Familiarity with space-based design techniques and radiation mitigation.
• Demonstrated history of 1st pass success with ASIC designs.

Typical Education/Experience

Entry Level (Level 1): Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, engineering technology, computer science, engineering data science, mathematics, physics, or chemistry (e.g., Bachelor), or an equivalent combination of technical education and experience or non-US equivalent qualifications.

Associate (Level 2): Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, engineering technology, computer science, engineering data science, mathematics, physics or chemistry (e.g., Bachelor) and typically 2 or more years' related work experience or an equivalent combination of technical education and experience or non-US equivalent qualifications.

Experienced (Level 3): Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, computer science, mathematics, physics or chemistry (e.g., Bachelor) and typically 5 or more years' related work experience or an equivalent combination of technical education and experience (e.g., PhD, Master+3 years' related work experience).

Key skills/competency

• ASIC Design
• FPGA Verification
• SystemVerilog
• UVM
• Static Timing Analysis
• RTL Design
• Digital ICs
• Functional Coverage
• Hardware Integration
• Scripting (Python/Perl)