Digital Design Engineer

What You Do At AMD Changes Everything

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

The Role

AMD is looking for motivated individuals seeking opportunities to solve complex problems in a fast-paced work environment. A successful candidate will be involved in the microarchitectural design and RTL implementation of AMD’s PCI Express (PCIe) and Compute Express Link (CXL) IP used for our next-generation servers, clients, GPU, and Semi-custom products. The team works in a collaborative environment with IP and system architects to define cutting edge features and solutions to enable execution of AMD’s aggressive product roadmap.

The Person

• Enjoys being in a collaborative environment where they can grow and learn with a sense of pride.
• Strong analytical thinking and problem-solving skills with excellent attention to detail.
• Eager to learn new designs techniques and new protocols.
• Must have good communication and interpersonal skills.

Key Responsibilities

• Microarchitectural design and RTL implementation of IP features.
• Participate in design specification and RTL code reviews.
• Collaborate with Design Verification team to execute on design features.
• Analyze RTL design for power and timing optimization.
• Establish and configure infrastructure for ELAB/CDC/Lint/UPFG flows.
• Deploy and manage integration environments for RTL design.
• Coordinate with integration teams to implement and optimize workflows.
• Configure and maintain P4 (Perforce) repositories and file structures.

Preferred Experience

• 8+ years of overall design experience in the ASIC industry.
• Familiar with industry standard high-speed protocols such as PCIe, CXL, SATA/SAS, USB.
• Knowledge in digital design and RTL implementation.
• Knowledge in synthesis and timing analysis to achieve timing closure.
• Experience in HDL (VHDL/Verilog), HVL (SystemVerilog) and SystemVerilog Assertions (SVA).
• Experience in design with multiple clock domains.
• Experience in low power design and methodology.
• Exposure to Makefile and other scripting languages like Perl, Python and Ruby.
• Experience with state-of-the-art industry standard Electronic Design Automation (EDA) Tools.

Academic Credentials

BS (or higher) degree in Electronics/Electrical or Computer Engineering desired.

Key skills/competency

• ASIC Design
• RTL Implementation
• PCIe/CXL Protocols
• Timing Analysis
• Power Optimization
• SystemVerilog
• EDA Tools
• Microarchitecture
• Verification Collaboration
• Scripting (Python/Perl)