Physical Design Engineer

About the Role

As a Physical Design Engineer at Annapurna Labs, part of AWS, you will be instrumental in developing a semiconductor platform based on revolutionary architecture. This role offers the opportunity to work on cutting-edge products within a disruptive system, directly contributing to the technologies powering the world's largest cloud provider. You'll operate in a dynamic, open, and fast-paced environment, helping AWS deliver highly reliable, scalable, and low-cost infrastructure solutions globally.

We are seeking talented physical design implementation engineers to join our exceptional Physical Design team, focused on creating Amazon’s next generation of products for the cloud market.

Key Job Responsibilities

• Daily involvement in all aspects of physical design chip development (RTL2GDS), including floorplanning, synthesis, clock tree synthesis, place and route, static timing analysis, power and noise analysis, physical verification testing, and equivalence checks.
• Actively engaged in design-backend convergence aspects and defining timing constraints.
• Taking full end-to-end responsibility for the physical design of macros and cluster levels, according to specifications, under challenging constraints, with a focus on optimizing power, area, and performance.
• Participation in the development of design flows, utilizing a variety of EDA tools and vendors such as Synopsys and Cadence.
• Engaged in defining implementation and signoff methodologies.

A Day in the Life

Your day will be filled with dynamic technical challenges that push the boundaries of semiconductor design. You'll collaborate with cross-functional teams, diving deep into intricate physical design processes, and translating complex architectural concepts into tangible technological solutions. Expect to engage in cutting-edge problem-solving that requires both creative thinking and precise technical execution.

About The Team

Our team is a passionate group of engineers dedicated to developing revolutionary semiconductor technologies. We thrive on innovation, collaboration, and the opportunity to create technologies that will impact global cloud computing infrastructure. We value diverse perspectives and believe that breakthrough innovations emerge from inclusive, supportive environments.

Basic Qualifications

• Understanding the entire physical design flow (“RTL to GDS”).
• Deep understanding of sign-off activities (timing and physical verification).
• Experience in advanced nodes technologies and implementation tools.
• Process and technology oriented.
• Leadership and mentoring skills.

Preferred Qualifications

• Full-chip experience (floor plan, layout, timing).
• Previous experience in high-speed designs.
• Previous experience in multi-voltage (low power) designs.

Key skills/competency

• Physical Design (RTL2GDS)
• Floorplanning
• Synthesis
• Clock Tree Synthesis (CTS)
• Place and Route
• Static Timing Analysis (STA)
• Power Analysis
• Physical Verification
• Equivalence Checks
• EDA Tools (Synopsys, Cadence)