ASIC Design Engineer

About Annapurna Labs & AWS

Annapurna Labs, an organization within AWS UC, designs innovative silicon and software that significantly accelerates cloud solutions. Customers rely on us to tackle previously unimaginable challenges. Our custom chips, accelerators, and software stacks enable us to address unprecedented technical hurdles and deliver world-changing results.

Amazon Web Services (AWS) is recognized as the world’s most comprehensive and widely adopted cloud platform. We pioneered cloud computing and continuously innovate, which is why leading startups and Global 500 companies trust our extensive suite of products and services to power their operations.

This role as an ASIC Design Engineer is based in Tel Aviv, with a potential option for relocation to the USA.

Key Job Responsibilities

• Integrate multiple subsystems into the top-level SOC, ensuring accurate clock, reset, functional, and DFT signal routing.
• As a key member of the ASIC design team, you will implement and deliver high-performance, area, and power-efficient RTL to meet design targets and specifications.
• Analyze design, microarchitecture, or architecture to make informed trade-offs based on feature requirements, power consumption, performance goals, or area constraints.
• Develop detailed micro-architecture, implement SystemVerilog RTL, and deliver synthesis/timing-clean designs complete with appropriate constraints.
• Perform comprehensive lint and clock domain crossing quality checks on the design.
• Collaborate closely with architects, other designers, verification teams, pre- and post-silicon validation teams, synthesis, timing, and back-end teams to successfully accomplish your tasks.

You Will Thrive In This Role If You

• Are familiar with scripting in Python.
• Are proficient with assertions.
• Possess strong debug skills to effectively analyze RTL test failures.
• Embody a "Learn and Be Curious" mindset, eager for continuous learning and exploration.

Working at AWS

AWS values diverse experiences and encourages all qualified candidates to apply, regardless of traditional career paths or alternative experiences. We foster work-life harmony, ensuring professional success does not compromise personal life, by striving for flexibility in our culture. Our inclusive team culture, driven by employee-led affinity groups, celebrates diversity and promotes continuous learning through events like Conversations on Race and Ethnicity (CORE) and AmazeCon. We are committed to mentorship and career growth, offering endless knowledge-sharing and resources to help you develop into a well-rounded professional.

About The Cloud-Scale Machine Learning Acceleration Team

Custom SoCs (System on Chip) are central to AWS Machine Learning servers. As part of the Cloud-Scale Machine Learning Acceleration team, you will be responsible for the design and optimization of hardware in our data centers, including AWS Inferentia, our custom-designed machine learning inference datacenter server. Our success relies on world-class server infrastructure, handling massive scale and rapid integration of emergent technologies. We are seeking an ASIC Design Engineer to trailblaze new technologies and architectures, while ensuring high design quality and making strategic trade-offs.

Our team is dedicated to supporting new members, offering a blend of experience levels and tenures. We cultivate an environment that prioritizes knowledge-sharing and mentorship, with senior members providing one-on-one guidance and constructive code reviews. We are invested in your career growth, assigning projects that develop your engineering expertise and empower you to undertake more complex challenges.

Basic Qualifications

• 3+ years in RTL design for SOC.
• 3+ years of VLSI engineering experience.
• 3+ years with code quality tools, including Spyglass, LINT, or CDC.

Preferred Qualifications

• Experience with Microarchitecture, SystemVerilog RTL, Assertions, and SDC constraints.
• Familiarity with data path design, interconnects, and AXI protocol.
• Good analytical, problem-solving, and communication skills.

Key skills/competency

• ASIC Design
• RTL Design
• SystemVerilog
• VLSI Engineering
• SOC Integration
• Clock Domain Crossing (CDC)
• Design For Test (DFT)
• Microarchitecture
• Python Scripting
• Timing Closure