Design Verification Engineer
@ Marvell Technology

Petah Tikva, Center District, Israel
$80,000
On Site
Full Time
Posted 21 days ago

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XXXXXXXX XXXXXXXXXXX XXXXXX***** @marvell.com
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Job Details

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Our innovative technology spans enterprise, cloud and AI, automotive, and carrier architectures, enabling new possibilities.

Your Team, Your Impact

Join a highly skilled, energetic team developing the next generation of high-end embedded, communication, and data center SOCs for the networking-data center industry. As a Design Verification Engineer, you will be part of the verification definition and implementation process, working closely with design, DV, validation, and software teams as well as IP teams/vendors.

What You Can Expect

  • Build an SV-UVMM environment for blocks.
  • Write stimuli (random tests & sequences), checkers, and coverage code.
  • Work as part of an agile verification team.

What We're Looking For

A B.Sc. student in Electrical or Software Engineering from one of Israel’s leading universities, available at least 2 days a week, with a hunger to learn and contribute to a fast-moving engineering team.

Additional Compensation and Benefits

Enjoy competitive compensation, great benefits, and a collaborative, transparent, and inclusive work environment. Explore more about working at Marvell on our Careers page.

Interview Integrity

Marvell emphasizes fair hiring practices. Candidates must not use AI tools during interviews to ensure authenticity. Note: This role may require clearance for export-controlled technology, subject to U.S. regulations.

Key skills/competency

SV-UVMM, verification, stimuli, checkers, coverage, SOC, simulation, embedded, testing, engineering

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How to Get Hired at Marvell Technology

🎯 Tips for Getting Hired

  • Customize your resume: Highlight verification and simulation skills.
  • Research Marvell: Understand their semiconductor solutions and culture.
  • Prepare for technical tests: Review SV-UVMM and verification basics.
  • Show hands-on experience: Emphasize collaboration in engineering projects.

📝 Interview Preparation Advice

Technical Preparation

Review SV-UVMM fundamentals.
Practice simulation coding exercises.
Study random test generation techniques.
Understand embedded SOC architecture.

Behavioral Questions

Describe teamwork in challenging projects.
Explain handling tight deadlines.
Share problem-solving experiences.
Discuss adapting to team feedback.

Frequently Asked Questions