Staff Engineer, PCIe PHY/Link Analysis
Samsung Semiconductor · San Jose, California, United States
Posted 26 days ago
or apply directly on Samsung Semiconductor's site. We never take the application ourselves.
Is this posting real?
- This role has been open
- 26 days Samsung Semiconductor's roles stay open a median of 44 days
- Reposted
- No
- Salary listed
- No 0% of Samsung Semiconductor's roles list one
- Ghost-job risk at Samsung Semiconductor
- high 34 stale, 1 reposted of 69 open
- Hiring momentum
- 93 roles opened in the last 90 days ↑ up vs. the prior 90 days
- Last confirmed on the employer's board
- 2026-09-17
Measured from postings appearing on and disappearing from Samsung Semiconductor's own greenhouse board since 2026-08-03. Full hiring picture for Samsung Semiconductor.
About this role
As a Staff Engineer in PCIe PHY/Link Analysis, you will develop and support cutting-edge Enterprise and Data Center SSD products, focusing on the PCIe protocol stack from the Physical Layer to the Transaction/Transport Layer. Your responsibilities include protocol stack analysis, link bring-up, debugging complex issues, and participating in compliance tests. You will also provide field support and collaborate with internal and external teams.
- benefits
- 5/5
- freshness
- 4/5
- career value
- 4/5
- role clarity
- 5/5
- pay transparency
- 0/5
Scored from the posting itself — how clearly the role is described, how much it says about pay and benefits, and how recently it was listed. Not a judgement of Samsung Semiconductor as an employer.
What you need
- BS in Computer/Electrical/Electronic Engineering or Computer Science and 8+ years of relevant experience or MS in the same fields with 5+ years of experience
- Deep proficiency with the PCIe protocol spanning the entire architecture
- Strong hands-on knowledge of LTSSM, link training/equalization, PCIe enumeration, flow control, replay/retry, and error handling
- Working knowledge of PHY-layer operation sufficient to root-cause link issues
- Solid experience in C/C++ for embedded systems
- Expertise with UART/JTAG/ICE debuggers
Nice to have
- Knowledge on SI/PI for PCIe
- Proficiency in NVMe, CXL, or SAS/SATA protocols
- Experience in both pre-silicon and post-silicon SoC validation
- Experience with PCIe power management
What you get
- Medical/Dental/Vision/401k
- 4+ weeks of paid time off a year
- Charitable giving match
- Stipend for fertility care or adoption
- Medical travel support
- Virtual vet care
Worth weighing
- Position requires up to 25% business travel
- No specific mention of remote work options
- Salary range provided but may vary by location and experience
Summarised from Samsung Semiconductor's posting. Read the full original.
Listed by Samsung Semiconductor on their greenhouse job board, last confirmed open on 2026-09-17. PitchMeAI is not the employer.
More roles at Samsung Semiconductor
- Senior Emulation EngineerSan Jose, California, United States
- Senior Physical Design EngineerSan Jose, California, United States
- Senior RTL Engineer, Memory Centric ComputingSan Jose, California, United States
- Manager, Learning & Development - Business EnablementSan Jose, California, United States
- Senior RTL Engineer, IO Die and Interconnect IPSan Jose, California, United States
- Executive Assistant & R&D Operations CoordinatorSan Jose, California, United States
- Principal Engineer, Architecture & Performance Research Engineer for Data Center and Agentic AI CPUSan Jose, California, United States
- Senior Engineer, Architecture & Performance Research Engineer for Data Center and Agentic AI CPUSan Jose, California, United States