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Samsung Semiconductor

Senior RTL Engineer, IO Die and Interconnect IP

Samsung Semiconductor · San Jose, California, United States

Posted 26 days ago

or apply directly on Samsung Semiconductor's site. We never take the application ourselves.

Is this posting real?

This role has been open
26 days
Samsung Semiconductor's roles stay open a median of 44 days
Reposted
No
Salary listed
No
0% of Samsung Semiconductor's roles list one
Ghost-job risk at Samsung Semiconductor
high
34 stale, 1 reposted of 69 open
Hiring momentum
93 roles opened in the last 90 days
↑ up vs. the prior 90 days
Last confirmed on the employer's board
2026-09-17

Measured from postings appearing on and disappearing from Samsung Semiconductor's own greenhouse board since 2026-08-03. Full hiring picture for Samsung Semiconductor.

About this role

As a Senior RTL Engineer in the AGI Computing Lab, you will develop RTL for IO die, integrating high-speed interconnect IP into a chiplet-based architecture. Your responsibilities include modifying interconnect IP, defining die-to-die interfaces, collaborating with verification engineers, and automating IP integration processes. You will work closely with various teams to ensure performance and interoperability while managing design trade-offs.

Our read on this posting3.6out of 5
benefits
5/5
freshness
4/5
career value
4/5
role clarity
5/5
pay transparency
0/5

Scored from the posting itself — how clearly the role is described, how much it says about pay and benefits, and how recently it was listed. Not a judgement of Samsung Semiconductor as an employer.

What you need

  • Bachelor’s with 5+ years, or Master’s with 3+ years, or PhD's with 0+ years of industry experience
  • Strong background in microarchitecture and RTL design for complex SoC and die integration
  • 5+ years of experience in RTL development (Verilog/SystemVerilog) for high-speed interconnect and IO subsystems
  • Hands-on experience integrating and configuring interconnect IP such as PCIe, CXL, UCIe, and die-to-die interfaces
  • Experience modifying or customizing third-party interconnect IP (e.g., PCIe controller, PIPE, or PHY interface) to meet die-level requirements
  • Familiarity with UCIe and chiplet-based, multi-die architectures and die-to-die interconnect

Nice to have

  • Experience in AI/ML workloads
  • Familiarity with agentic AI tools and frameworks

What you get

  • 4+ weeks of paid time off a year, plus holidays and sick leave
  • Medical/Dental/Vision/401k
  • Charitable giving match
  • Stipend for fertility care or adoption
  • Medical travel support
  • Virtual vet care for pets

Worth weighing

  • No specific salary listed, but a pay range is provided
  • Daily onsite presence required in San Jose, CA
  • The role involves significant collaboration across teams, which may impact individual work style

Summarised from Samsung Semiconductor's posting. Read the full original.

Listed by Samsung Semiconductor on their greenhouse job board, last confirmed open on 2026-09-17. PitchMeAI is not the employer.

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