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Samsung Semiconductor

Senior HSIO Digital Design Engineer

Samsung Semiconductor · San Jose, California, United States

Posted about 3 months ago

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Is this posting real?

This role has been open
81 days
Samsung Semiconductor's roles stay open a median of 80 days
Reposted
No
Salary listed
No
0% of Samsung Semiconductor's roles list one
Ghost-job risk at Samsung Semiconductor
high
66 stale, 1 reposted of 69 open
Hiring momentum
93 roles opened in the last 90 days
↑ up vs. the prior 90 days
Last confirmed on the employer's board
2026-10-23

Measured from postings appearing on and disappearing from Samsung Semiconductor's own greenhouse board since 2026-08-03. Full hiring picture for Samsung Semiconductor.

About this role

The Senior HSIO Digital Design Engineer will focus on next-generation High-Speed I/O design for Samsung's AI production platforms. Daily responsibilities include developing high-speed I/O PHY IP, collaborating with system and analog teams, and ensuring a strong understanding of digital design flows and interconnect protocols. The role requires hands-on experience and a solid grasp of signal and power integrity modeling for high-speed designs.

Our read on this posting2.4out of 5
benefits
3/5
freshness
1/5
career value
4/5
role clarity
4/5
pay transparency
0/5

Scored from the posting itself — how clearly the role is described, how much it says about pay and benefits, and how recently it was listed. Not a judgement of Samsung Semiconductor as an employer.

What you need

  • BS in Electrical Engineering with 5+ years of experience, MS in Electrical Engineering with 3+ years of experience, or PhD in Electrical Engineering
  • 3+ years of industry experience specializing in digital design for die-to-die interfaces or similar high-speed I/O technologies
  • Hands-on experience in High-Speed I/O PHY IP development
  • Strong understanding of high-speed serial interconnect protocols and associated design trade-offs
  • Solid understanding of how analog and mixed-signal design and verification impact digital-on-top development flows
  • Knowledge of Signal Integrity (SI) and Power Integrity (PI) modeling for High-Speed I/O designs

Nice to have

  • Understanding of SoC protocols including AXI/CHI/CXS.B/CXL/PCIE/UA-Link
  • Familiarity with HSIO PHY layers protocols and architectures

What you get

  • Medical/Dental/Vision/401k
  • 4+ weeks of paid time off a year, plus holidays and sick leave
  • Stipend for fertility care or adoption, caregiver support, and medical travel support
  • On-demand apps and free confidential therapy sessions
  • Onsite Café and gym, plus virtual classes
  • Flexible work environment

Worth weighing

  • No specific salary details for the role beyond the range provided
  • Role requires onsite work at the San Jose headquarters
  • High application volume may affect candidate experience

Summarised from Samsung Semiconductor's posting. Read the full original.

Listed by Samsung Semiconductor on their greenhouse job board, last confirmed open on 2026-10-23. PitchMeAI is not the employer.

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