Principal Engineer, SOC Design
Samsung Semiconductor · San Jose, California, United States
Posted 13 days ago
or apply directly on Samsung Semiconductor's site. We never take the application ourselves.
Is this posting real?
- This role has been open
- 13 days Samsung Semiconductor's roles stay open a median of 44 days
- Reposted
- No
- Salary listed
- No 0% of Samsung Semiconductor's roles list one
- Ghost-job risk at Samsung Semiconductor
- high 34 stale, 1 reposted of 69 open
- Hiring momentum
- 93 roles opened in the last 90 days ↑ up vs. the prior 90 days
- Last confirmed on the employer's board
- 2026-09-17
Measured from postings appearing on and disappearing from Samsung Semiconductor's own greenhouse board since 2026-08-03. Full hiring picture for Samsung Semiconductor.
About this role
As a Principal Engineer in SOC Design at Samsung's DRAM Development Lab, you will be responsible for the architectural definitions and micro architecture of subsystems and chip levels. Your role involves integrating third-party IPs, conducting logic design and RTL implementation, and collaborating with architects and verification engineers to ensure sound design at the SoC level, particularly for emerging applications in machine learning and data analytics.
- benefits
- 4/5
- freshness
- 4/5
- career value
- 4/5
- role clarity
- 4/5
- pay transparency
- 0/5
Scored from the posting itself — how clearly the role is described, how much it says about pay and benefits, and how recently it was listed. Not a judgement of Samsung Semiconductor as an employer.
What you need
- Bachelors in Electrical, Computer Science or related with 20+ years of experience or Masters in Electrical, Computer Science or related Science with 18+ years of Industry Experience or PhD in Electrical, Computer Science or related Science with 15+ years of Industry experience
- Hands on knowledge & experience in ASIC design flow from design to tape out
- Experience & Good knowledge in ATE vector generation, testing and silicon bring up
- Experience in the commercial IPs such as UCIe, CPU, Ethernet, and DDR interfaces
- Good understanding of PPA (performance, power, and area) trade-offs
- Experience in SoC level synthesis, timing analysis, lint check, CDC checks
Nice to have
- Highly motivated with good verbal and written communication skills
- You’re inclusive, adapting your style to the situation and diverse global norms of our people
- An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding
- You’re collaborative, building relationships, humbly offering support and openly welcoming approaches
- Innovative and creative, you proactively explore new ideas and adapt quickly to change
What you get
- 4+ weeks of paid time off a year, plus holidays and sick leave
- Medical/Dental/Vision/401k
- Charitable giving match
- Stipend for fertility care or adoption, medical travel support, and virtual vet care
- On-demand apps and free confidential therapy sessions
- Onsite Café and gym, plus virtual classes
Worth weighing
- Daily onsite presence required at San Jose or Folsom office
- No specific salary details provided beyond the range
- Role may involve legacy technology and integration challenges with third-party IPs
Summarised from Samsung Semiconductor's posting. Read the full original.
Listed by Samsung Semiconductor on their greenhouse job board, last confirmed open on 2026-09-17. PitchMeAI is not the employer.
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