Principal Design Verification Engineer
SambaNova Systems · San Jose, California, United States
Posted about a month ago
or apply directly on SambaNova Systems's site. We never take the application ourselves.
Is this posting real?
- This role has been open
- 30 days SambaNova Systems's roles stay open a median of 33 days
- Reposted
- No
- Salary listed
- No 0% of SambaNova Systems's roles list one
- Ghost-job risk at SambaNova Systems
- high 21 stale, 2 reposted of 57 open
- Hiring momentum
- 68 roles opened in the last 90 days ↑ up vs. the prior 90 days
- Last confirmed on the employer's board
- 2026-09-17
Measured from postings appearing on and disappearing from SambaNova Systems's own greenhouse board since 2026-08-03. Full hiring picture for SambaNova Systems.
About this role
As a Principal Design Verification Engineer at SambaNova, you will lead the verification process for the reconfigurable dataflow silicon used in machine learning and AI systems. Your responsibilities will include developing test plans, testbench architecture, and coverage models, as well as mentoring other engineers and advancing verification methodologies. You will collaborate with cross-functional teams to ensure the quality and reliability of the silicon before production.
- benefits
- 5/5
- freshness
- 4/5
- career value
- 5/5
- role clarity
- 5/5
- pay transparency
- 0/5
Scored from the posting itself — how clearly the role is described, how much it says about pay and benefits, and how recently it was listed. Not a judgement of SambaNova Systems as an employer.
What you need
- BS or MS in EE, CS, or CE with 7+ years of industry experience in ASIC design verification
- Deep hands-on expertise in SystemVerilog and SVA with a standard methodology (UVM, OVM, or VMM)
- Scripting skills in Python and C/C++
- Full-cycle DV ownership from test plan through tape-out on at least one complex ASIC or major subsystem
- Experience verifying digital logic in a CPU, GPU, SoC, or comparably complex ASIC
- Track record of debugging hard, intermittent, or low-reproducibility pre-silicon failures to root cause
Nice to have
- MS or PhD in EE, CS, or CE with 10+ years of experience in ASIC design verification
- Depth in high-speed I/O verification: protocol-level verification of PCIe or Ethernet, and memory subsystems such as HBM or DDR
- Performance verification methodology: building performance benches and analyzing results
- Formal verification and assertion-based methods
- Experience evaluating, integrating, and validating third-party verification IP
What you get
- Competitive total rewards package including base salary and equity
- 95% premium coverage for employee medical insurance
- 77% premium coverage for dependents
- Health Savings Account (HSA) with employer contribution
- Dental, Vision, Short/Long term Disability, Basic Life, Voluntary Life, and AD&D insurance plans
- Flexible Spending Account (FSA) options
Worth weighing
- No specific mention of remote work options
- Base salary range provided is $180,000 — $255,000 USD, which may vary based on experience
- The role emphasizes technical leadership without formal authority, which may not suit all candidates
Summarised from SambaNova Systems's posting. Read the full original.
Listed by SambaNova Systems on their greenhouse job board, last confirmed open on 2026-09-17. PitchMeAI is not the employer.
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