Head of Test Development Engineering
Ethernovia, Inc. · San Jose, CA
Posted about a month ago · $220,000 - $280,000
or apply directly on Ethernovia, Inc.'s site. We never take the application ourselves.
Is this posting real?
- This role has been open
- 30 days Ethernovia, Inc.'s roles stay open a median of 45 days
- Reposted
- No
- Salary listed
- Yes 33% of Ethernovia, Inc.'s roles list one
- Ghost-job risk at Ethernovia, Inc.
- high 22 stale, 0 reposted of 27 open
- Hiring momentum
- 33 roles opened in the last 90 days ↑ up vs. the prior 90 days
- Last confirmed on the employer's board
- 2026-09-17
Measured from postings appearing on and disappearing from Ethernovia, Inc.'s own greenhouse board since 2026-08-03. Full hiring picture for Ethernovia, Inc..
About this role
The Head of Test Development Engineering at Ethernovia will oversee the transition of products from new product introduction (NPI) to high-volume manufacturing (HVM). This role involves hands-on leadership in semiconductor test development, ensuring robust test architecture and methodologies are in place for high-speed Ethernet switch and PHY products, while managing test labs and vendor relationships.
- benefits
- 3/5
- freshness
- 4/5
- career value
- 4/5
- role clarity
- 4/5
- pay transparency
- 5/5
Scored from the posting itself — how clearly the role is described, how much it says about pay and benefits, and how recently it was listed. Not a judgement of Ethernovia, Inc. as an employer.
What you need
- Bachelor's or Master's degree in Electrical Engineering or a related technical field
- 12+ years of experience in fabless semiconductor operations, specifically for complex, high-performance SOCs or networking ICs
- Expert in ATE 93K platform and Smartest, test method libraries and design of test hardware with robust SI/PI for wafer and final test
- Expertise with iJTAG, Scan (SSN), MBIST, Sensor, SerDes, LSIO/HSIO testing, security fusing and test automation for multi-site (x8, x16) parallel testing
- Expert in SLT testing using bare-metal, functional DVFS and benchmark testing and expert in multi-site handler automation framework and test log standards
- Experience with Analog characterizing high-speed communication chips on ATE and System to ensure all IO parameters are characterized and tested
Nice to have
- Experience with simulation, pattern generation, and pattern conversion
- Experience delivering high speed SerDes products to Tier-1 automotive OEMs
- Experience negotiating with and managing hardware vendors and OSATs
What you get
- Pre IPO stock options
- Cutting edge technology
- World class team
- Competitive base salary
- Flexible hours
- Medical, dental and vision insurance for employees
Worth weighing
- No salary listed in the posting, but a range is provided
- The role requires extensive experience in a highly specialized field, which may limit the candidate pool
- The position is based in San Jose, CA, which may involve relocation or commuting considerations
Summarised from Ethernovia, Inc.'s posting. Read the full original.
Listed by Ethernovia, Inc. on their greenhouse job board, last confirmed open on 2026-09-17. PitchMeAI is not the employer.
More roles at Ethernovia, Inc.
- Head of Product Development EngineeringSan Jose, CA
- Senior Developer-Python (Test Automation)Pune
- Senior ASIC Design Verification EngineerSan Jose, CA
- Senior ASIC (Front-End) Design EngineerSan Jose, CA