Digital Flow Enablement Solutions Architect
Cadence · San Jose, CA
- On site
- Full-time
- $292,500 / year
- San Jose, CA
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Digital Flow Enablement Solutions Architect
Cadence · San Jose, CA
Avery Quinn
Hiring Manager · h•••••@cadence.wd1.myworkdayjobs.com
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Subject: Interested in the Digital Flow Enablement Solutions Architect role at Cadence
Hi Avery — I came across the Digital Flow Enablement Solutions Architect opening and wanted to reach out directly. I've spent the last few years doing exactly this kind of work, and Cadence stood out because…
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Not recommended alone — most applicants never hear back.
Job highlights
- Lead customer engagements on library optimization.
- Enable RTL to GDS flows and methodologies.
- Develop and validate timing and physical views.
- Work with advanced nodes and EDA tools.
- Requires strong customer interaction skills.
About the role
Digital Flow Enablement Solutions Architect
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Locations
Remote role but must be currently located in the US.
The Position Involves
- Leading customer engagements on standard cell library optimization and RTL->GDS enablement, including techLEF creation and updates, mapping files, and general flow development.
- Interfacing with customers regarding digital flow enablement and methodologies, including:
- Timing characterization, including sensitivity modeling,
- Physical view generation (LEF, GDS, abstracts, etc)
- Logical view generation (LIB, CDL, Spectre, etc)
- Technology LEF creation for digital tools
- MSOA flows
- Performing design of experiments and running Genus/Innovus to validate techLEF correctness and library performance and DRC correctness
- Tempus timing flow development and validation
- Working closely with R&D on tools and methodology improvements
- Other digital P&R tasks as needed by the group
Processes nodes range from 1.4nm to 350nm, with the majority of work at GAA advanced nodes.
Position Requirements
- Bachelor’s degree with at least 12-16 years of design/EDA experience or Master’s degree with at least 10 years of experience. Master’s degree preferred.
- Knowledge of standard cell and IO design, optimization and characterization methodology including LLE/LDE effects
- Excellent digital simulation and debug skills
- Experience with techLEF development at advanced nodes a must
- Understanding of Liberty (.lib), Verilog & other views, such as NLDM, CCS & ECSM
- Strong knowledge of Digital Design flows and Static Timing Analysis
- Prior experience with ASIC digital implementation flows and EDA tools is required
- Experience with advanced nodes (5nm and below) required.
- Good programming knowledge in Unix, Shell scripting, perl and importantly TCL
- Strong customer-facing communication and problem solving skills
- Strong personal drive for continuous learning and expanding professional skill sets
- Excellent verbal and written communication skills
Familiar With EDA Tool
- Characterization: Liberate, Liberate MX, Liberate AMS
- Simulators: Spectre, AMS, Xcelium
- Digital: Genus, Innovus, Tempus, Voltus, PrimeTime etc
Salary and Benefits
The annual salary range for California is $157,500 to $292,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
We’re doing work that matters. Help us solve what others can’t.
Key skills/competency
- Digital Flow Enablement Solutions Architect
- Standard Cell Library Optimization
- RTL to GDS Enablement
- TechLEF Creation
- Timing Characterization
- Physical View Generation
- Digital Design Flows
- Static Timing Analysis
- ASIC Implementation
- Advanced Nodes (5nm and below)
Skills & topics
- Digital Flow Enablement
- Solutions Architect
- EDA
- ASIC Design
- Library Optimization
- RTL to GDS
- TechLEF
- Timing Analysis
- Advanced Nodes
- TCL Scripting
- Remote
- US
How to get hired
- Tailor your resume: Highlight your expertise in RTL to GDS, techLEF development, and advanced nodes (5nm and below).
- Showcase EDA tool proficiency: Emphasize experience with Genus, Innovus, Tempus, Liberate, Spectre, and TCL scripting.
- Demonstrate customer-facing skills: Provide examples of successful customer engagements and problem-solving.
- Prepare for technical interviews: Be ready to discuss digital design flows, static timing analysis, and characterization methodologies.
- Express continuous learning: Showcase your drive for expanding professional skill sets and staying current with EDA advancements.
Technical preparation
Master standard cell and IO design principles.,Practice techLEF development for advanced nodes.,Gain proficiency in Genus, Innovus, and Tempus.,Sharpen TCL scripting and Unix shell skills.
Behavioral questions
Describe a complex customer problem you solved.,How do you stay updated on EDA advancements?,Share an experience collaborating with R&D.,How do you manage competing priorities in projects?
Prefer to apply the usual way?
Not recommended alone — most applicants never hear back. Email the hiring manager first.
Frequently asked questions
- What is the work arrangement for the Digital Flow Enablement Solutions Architect role at Cadence?
- This is a remote role. However, candidates must be currently located within the United States to be considered for this Digital Flow Enablement Solutions Architect position at Cadence.
- What are the primary responsibilities of a Digital Flow Enablement Solutions Architect at Cadence?
- The Digital Flow Enablement Solutions Architect at Cadence leads customer engagements focused on standard cell library optimization and RTL to GDS enablement. This includes techLEF creation, mapping files, general flow development, timing characterization, and physical/logical view generation.
- What specific EDA tools are commonly used in this role at Cadence?
- Cadence utilizes a range of EDA tools for this Digital Flow Enablement Solutions Architect role, including characterization tools like Liberate and Liberate MX, simulators such as Spectre and Xcelium, and digital implementation tools like Genus, Innovus, and Tempus.
- What level of experience is required for the Digital Flow Enablement Solutions Architect position?
- A Bachelor's degree with 12-16 years of design/EDA experience or a Master's degree with 10+ years of experience is required for this Digital Flow Enablement Solutions Architect role at Cadence. A Master's degree is preferred.
- Is experience with advanced semiconductor nodes necessary for this role?
- Yes, experience with advanced nodes, specifically 5nm and below, is required for the Digital Flow Enablement Solutions Architect role. Familiarity with GAA advanced nodes is also highly relevant.
- What programming and scripting skills are important for this role at Cadence?
- Proficiency in Unix, Shell scripting, Perl, and especially TCL is essential for the Digital Flow Enablement Solutions Architect role at Cadence, as these are used for flow development and tool interaction.
- What is the typical salary range for a Digital Flow Enablement Solutions Architect at Cadence?
- The annual salary range for this Digital Flow Enablement Solutions Architect position in California is $157,500 to $292,500. Actual compensation may vary based on qualifications, skill level, competencies, and work location.
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