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Tenstorrent

Physical Design Engineer, PnR

Tenstorrent · Austin, Texas, United States; Fort Collins, Colorado, United States; Santa Clara, California, United States

Posted about 3 months ago · $100k - $500k

or apply directly on Tenstorrent's site. We never take the application ourselves.

Is this posting real?

This role has been open
80 days
Tenstorrent's roles stay open a median of 81 days
Reposted
No
Salary listed
Yes
64% of Tenstorrent's roles list one
Ghost-job risk at Tenstorrent
high
131 stale, 1 reposted of 140 open
Hiring momentum
189 roles opened in the last 90 days
↑ up vs. the prior 90 days
Last confirmed on the employer's board
2026-10-23

Measured from postings appearing on and disappearing from Tenstorrent's own greenhouse board since 2026-08-03. Full hiring picture for Tenstorrent.

About this role

As a Physical Design Engineer at Tenstorrent, you will be responsible for implementing high-performance partitions for an AI SoC, overseeing the complete flow from synthesis to tapeout. You will collaborate with a cross-functional team to resolve design challenges and ensure successful physical verification signoff. This hybrid role allows you to work from Austin, TX, Santa Clara, CA, or Fort Collins, CO, and is open to candidates of various experience levels.

Our read on this posting3.0out of 5
benefits
1/5
freshness
1/5
career value
4/5
role clarity
4/5
pay transparency
5/5

Scored from the posting itself — how clearly the role is described, how much it says about pay and benefits, and how recently it was listed. Not a judgement of Tenstorrent as an employer.

What you need

  • Experienced with synthesis and place-and-route flows, especially using Synopsys Design Compiler / Fusion Compiler and IC Compiler II.
  • Comfortable in a small, cross-functional physical design team, owning a block or subsystem and partnering on tapeout milestones with clear communication and accountability.
  • Execute synthesis, PNR, and STA for assigned partitions of a complex AI SoC.
  • Help close EM/IR, ensure UPF power intent is consistent with implementation, and drive LEC and physical verification signoff for your partitions in coordination with methodology owners.
  • Work closely with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues across your blocks.

Nice to have

  • Extra depth in areas such as UPF/multi-voltage power domains, SoC interface IP integration (e.g. I3C, UART), signoff breadth (DRC/LVS, EM/IR, LEC/Formality), multi-clock/CDC-aware implementation, PLL/DLL integration, and DFT-aware physical implementation (OCC/MBIST).

What you get

  • Compensation ranges from $100k - $500k including base and variable compensation targets.
  • Highly competitive compensation package and benefits.

Worth weighing

  • The role requires access to U.S. export-controlled technology, which may affect eligibility based on citizenship or residency status.
  • No specific benefits listed beyond compensation.

Summarised from Tenstorrent's posting. Read the full original.

Listed by Tenstorrent on their greenhouse job board, last confirmed open on 2026-10-23. PitchMeAI is not the employer.

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