Senior Physical Design Engineer
Samsung Semiconductor · San Jose, California, United States
Posted about 2 months ago
or apply directly on Samsung Semiconductor's site. We never take the application ourselves.
Is this posting real?
- This role has been open
- 64 days Samsung Semiconductor's roles stay open a median of 80 days
- Reposted
- No
- Salary listed
- No 0% of Samsung Semiconductor's roles list one
- Ghost-job risk at Samsung Semiconductor
- high 66 stale, 1 reposted of 69 open
- Hiring momentum
- 93 roles opened in the last 90 days ↑ up vs. the prior 90 days
- Last confirmed on the employer's board
- 2026-10-23
Measured from postings appearing on and disappearing from Samsung Semiconductor's own greenhouse board since 2026-08-03. Full hiring picture for Samsung Semiconductor.
About this role
As a Senior Physical Design Engineer in the AGI Computing Lab, you will be responsible for the physical implementation of memory-centric computing IP and SoC partitions, overseeing processes from RTL netlist to GDSII. Your role includes driving performance, power, and area convergence, conducting static timing analysis, and collaborating with hardware and software engineers to address challenges in AI/ML workloads. You will also develop automation flows using scripting languages to enhance design efficiency.
- benefits
- 4/5
- freshness
- 4/5
- career value
- 4/5
- role clarity
- 4/5
- pay transparency
- 0/5
Scored from the posting itself — how clearly the role is described, how much it says about pay and benefits, and how recently it was listed. Not a judgement of Samsung Semiconductor as an employer.
What you need
- Bachelor’s with 5+ years, or Master’s with 3+ years, or PhD's with 0+ years of industry experience
- Strong background in digital physical design and VLSI implementation
- 5+ years of experience in physical design implementation — synthesis, floorplanning, place-and-route, clock tree synthesis, and timing closure — for complex ASIC/SoC designs
- Proficiency with industry-standard EDA tools such as Synopsys Fusion Compiler/ICC2, Cadence Innovus, PrimeTime, and StarRC
- Experience with static timing analysis and constraint (SDC) development, low-power design (UPF/CPF), and power, IR-drop, and electromigration analysis
- Experience with physical verification (DRC, LVS, antenna) and tapeout on advanced FinFET process nodes
What you get
- 4+ weeks of paid time off a year, plus holidays and sick leave
- Medical/Dental/Vision/401k
- Charitable giving match
- Stipend for fertility care or adoption, medical travel support, and virtual vet care
- On-demand apps and free confidential therapy sessions
- Onsite Café and gym, plus virtual classes
Worth weighing
- Daily onsite presence required at the San Jose office
- No specific mention of the technology stack beyond EDA tools and design processes
- Role involves significant collaboration with both hardware and software teams, which may require strong interpersonal skills
Summarised from Samsung Semiconductor's posting. Read the full original.
Listed by Samsung Semiconductor on their greenhouse job board, last confirmed open on 2026-10-23. PitchMeAI is not the employer.
More roles at Samsung Semiconductor
- Manager, People Analytics & Workforce IntelligenceSan Jose, California, United States
- Senior Staff Engineer, Design VerificationSan Jose, California, United States
- Staff Engineer, Memory Systems ArchitectureSan Jose, California, United States
- Staff Engineer, High-Speed I/O Analog-Mixed CircuitSan Jose, California, United States
- Senior Manager, Memory SalesSan Jose, California, United States
- Senior Manager, Memory SalesWashington
- Director Federal Government RelationsWashington, District of Columbia, United States
- Director, Foundry Customer EngineeringSan Jose, California, United States