Senior RTL Design Engineer
SambaNova Systems · Austin, Texas, United States; San Jose, California, United States
Posted 27 days ago
or apply directly on SambaNova Systems's site. We never take the application ourselves.
Is this posting real?
- This role has been open
- 27 days SambaNova Systems's roles stay open a median of 33 days
- Reposted
- No
- Salary listed
- No 0% of SambaNova Systems's roles list one
- Ghost-job risk at SambaNova Systems
- high 21 stale, 2 reposted of 57 open
- Hiring momentum
- 68 roles opened in the last 90 days ↑ up vs. the prior 90 days
- Last confirmed on the employer's board
- 2026-09-17
Measured from postings appearing on and disappearing from SambaNova Systems's own greenhouse board since 2026-08-03. Full hiring picture for SambaNova Systems.
About this role
As a Senior RTL Design Engineer at SambaNova, you will be responsible for designing component units of the Reconfigurable Dataflow Unit (RDU) ASICs used in AI acceleration systems. Your role involves owning blocks within larger subsystems, contributing to microarchitecture specifications, and managing the RTL design process through implementation and silicon bring-up, collaborating closely with other engineering teams.
- benefits
- 4/5
- freshness
- 4/5
- career value
- 4/5
- role clarity
- 4/5
- pay transparency
- 0/5
Scored from the posting itself — how clearly the role is described, how much it says about pay and benefits, and how recently it was listed. Not a judgement of SambaNova Systems as an employer.
What you need
- B.S. in Electrical Engineering, Computer Engineering, or Computer Science
- 5+ years of experience in ASIC RTL design
- Solid foundation in computer architecture and digital logic design
- Strong SystemVerilog RTL design skills for high-speed, high-performance ASICs
- Experience making design decisions that trade off power, performance, and area
- Knowledge of industry-standard interconnects and protocols including AXI, PCIe, Ethernet, and HBM or DDR
Nice to have
- M.S. or Ph.D. in Electrical Engineering, Computer Engineering, or Computer Science
- Exposure to a full ASIC development cycle through tape-out and production silicon
- Interest in or knowledge of AI workload acceleration techniques
- Experience with low-power design techniques such as clock gating and DVFS at advanced process nodes
- Exposure to emulation or FPGA prototyping platforms for pre-silicon validation
What you get
- Competitive total rewards package including base salary and equity
- 95% premium coverage for employee medical insurance
- 77% premium coverage for dependents
- Health Savings Account (HSA) with employer contribution
- Dental, Vision, Short/Long term Disability, Basic Life, Voluntary Life, and AD&D insurance plans
- Flexible Spending Account (FSA) options like Health Care, Limited Purpose, and Dependent Care
Worth weighing
- Base salary range is $120,000 - $200,000, which may vary based on experience and negotiation
- The role requires a strong technical background in ASIC design, which may limit applicants without such experience
- The position involves collaboration with various engineering teams, which may require strong interpersonal skills
Summarised from SambaNova Systems's posting. Read the full original.
Listed by SambaNova Systems on their greenhouse job board, last confirmed open on 2026-09-17. PitchMeAI is not the employer.
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