Principal RTL Design Engineer
SambaNova Systems · San Jose, California, United States
Posted about a month ago
or apply directly on SambaNova Systems's site. We never take the application ourselves.
Is this posting real?
- This role has been open
- 30 days SambaNova Systems's roles stay open a median of 33 days
- Reposted
- No
- Salary listed
- No 0% of SambaNova Systems's roles list one
- Ghost-job risk at SambaNova Systems
- high 21 stale, 2 reposted of 57 open
- Hiring momentum
- 68 roles opened in the last 90 days ↑ up vs. the prior 90 days
- Last confirmed on the employer's board
- 2026-09-17
Measured from postings appearing on and disappearing from SambaNova Systems's own greenhouse board since 2026-08-03. Full hiring picture for SambaNova Systems.
About this role
As a Principal RTL Design Engineer at SambaNova Systems, you will lead the microarchitecture and RTL implementation for a major block or subsystem of the Reconfigurable Dataflow Unit, focusing on high-performance ASIC design. Your role involves defining specifications, driving timing closure, and collaborating with various engineering teams to enhance application-level performance. You will also mentor junior engineers and set technical standards within the design team.
- benefits
- 5/5
- freshness
- 4/5
- career value
- 5/5
- role clarity
- 5/5
- pay transparency
- 0/5
Scored from the posting itself — how clearly the role is described, how much it says about pay and benefits, and how recently it was listed. Not a judgement of SambaNova Systems as an employer.
What you need
- BS or MS in EE, CE, or CS
- 7+ years of industry experience in ASIC RTL design
- Mastery of synthesizable SystemVerilog for high-speed ASICs
- High-frequency design experience including datapath pipelining and critical-path restructuring
- Deep foundation in computer architecture and digital logic design
- Ownership of a complex block or subsystem from microarchitecture specification through tape-out on at least one production ASIC
Nice to have
- Depth in one RDU domain: compute and dataflow datapath, on-chip network and interconnect, or memory subsystem
- Industry-standard interconnects and protocols: AXI, PCIe, Ethernet, HBM/DDR
- AI and ML workload acceleration techniques
- Formal property checking applied to design intent
- Advanced TSMC nodes and multi-die or chiplet design
What you get
- 95% premium coverage for employee medical insurance
- 77% premium coverage for dependents
- Health Savings Account (HSA) with employer contribution
- Dental and Vision insurance
- Short/Long term Disability insurance
- Basic Life, Voluntary Life, and AD&D insurance plans
Worth weighing
- Base salary range is $180,000 to $255,000, which may vary based on experience and qualifications.
- The role requires significant technical leadership without formal authority, which may be challenging for some candidates.
Summarised from SambaNova Systems's posting. Read the full original.
Listed by SambaNova Systems on their greenhouse job board, last confirmed open on 2026-09-17. PitchMeAI is not the employer.
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