Principal ASIC Physical Design Engineer
K2 Space · United States - Remote
Posted about 3 months ago · $190,000 – $280,000
or apply directly on K2 Space 's site. We never take the application ourselves.
Is this posting real?
- This role has been open
- 81 days K2 Space 's roles stay open a median of 81 days
- Reposted
- No
- Salary listed
- Yes 78% of K2 Space 's roles list one
- Ghost-job risk at K2 Space
- high 217 stale, 0 reposted of 220 open
- Hiring momentum
- 244 roles opened in the last 90 days ↑ up vs. the prior 90 days
- Last confirmed on the employer's board
- 2026-10-23
Measured from postings appearing on and disappearing from K2 Space 's own greenhouse board since 2026-08-03. Full hiring picture for K2 Space .
About this role
The Principal ASIC Physical Design Engineer will lead the implementation of complex SoCs for next-generation satellite systems, managing the full physical design flow from RTL handoff to GDSII. This role involves collaboration with various teams, managing external partners, and ensuring successful silicon outcomes using advanced FinFET technologies. The engineer will contribute to developing state-of-the-art mixed-signal SoCs that will be deployed in space, with responsibilities including timing closure, PPA optimization, and supporting chip bring-up.
- benefits
- 1/5
- freshness
- 1/5
- career value
- 5/5
- role clarity
- 5/5
- pay transparency
- 5/5
Scored from the posting itself — how clearly the role is described, how much it says about pay and benefits, and how recently it was listed. Not a judgement of K2 Space as an employer.
What you need
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field
- 10+ years of experience in ASIC physical design for high-performance SoCs
- Proven end-to-end expertise in RTL-to-GDSII flows using industry tools (Synopsys, Cadence, or Siemens)
- Strong hands-on experience with timing closure, IR drop analysis, and ECO implementation
- Deep understanding of physical design constraints for multi-clock, multi-voltage, and hierarchical SoCs
- Experience with advanced FinFET process nodes
Nice to have
- Exposure to radiation-hardened or space-qualified ASICs
- Experience with chip-package co-design or advanced packaging (2.5D/3D)
- Familiarity with physical design service vendor management or offshore collaboration
- Experience driving tapeouts through TSMC
- Experience with Gate-All-Around technologies
What you get
- Base salary range for this role is $190,000 – $280,000 + equity in the company
- Comprehensive benefits package including paid time off, medical/dental/vision coverage, life insurance, paid parental leave, and many other perks.
Worth weighing
- No specific mention of remote work policies beyond location being remote.
- The role requires managing external partners, which may involve additional coordination challenges.
- The company is in a high-growth phase, which could mean a fast-paced and potentially high-pressure work environment.
Summarised from K2 Space 's posting. Read the full original.
Listed by K2 Space on their greenhouse job board, last confirmed open on 2026-10-23. PitchMeAI is not the employer.
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